1. Field of the Invention
This invention relates to a thin film transistor (hereinafter referred to as TFT) and a method of manufacturing the same, and in particular to a technique for obtaining a TFT having a high withstand voltage and a low leak current characteristic by a simple manufacturing process.
2. Prior Art
Thin film transistors, which are active elements having semiconductor thin film layers formed on an insulating substrate, various applications including transmission-type liquid crystal displays of large surface area and contact-type image sensors are being aimed at. Particular attention is being centered on devices based on polycrystalline silicon. As an active element, the requirements to be met by a TFT include:                A. a high mutual conductance, and        B. a high dielectric withstand voltage between the source and the drain.        
The mutual conductance referred to here is a concept which corresponds to the amplification factor of a transistor or a vacuum tube, and is defined, for VDS=constant, as (dID/dVGS), where ID is the drain current, VGS is the gate control voltage, and VDS is the source-drain voltage.
The reason why a high dielectric withstand voltage is required between the source and the drain of an active TFT is that no leak current should flow between the source and the drain as a result of a voltage applied across the two. More specifically, the TFT must have a voltage withstand characteristic, with respect to a voltage applied between the source and the drain, such that no leak current (called OFF current) is allowed to flow between the source and the drain when the TFT is in the OFF state, i.e. the state in which no electric current should be allowed to flow between the source and the drain, and in order to achieve this it is necessary for the source-drain dielectric withstand voltage to be made high.
To satisfy the above-mentioned requirements, various ideas, including an LDD (Light Dope Drain) structure and a gate offset structure have been proposed. However, the present situation is that it is not possible with a simple self alignment process to realize completely a structure which satisfies the above requirements A and B.
FIG. 1(E) of the accompanying drawings schematically illustrates the construction of a known TFT that has been proposed to realize a high withstand voltage and a low leak current characteristic. This TFT is of a so-called gate offset structure, and, as shown in FIG. 1(E), comprises a source region 17, a channel forming region 18 and a drain region 19 along with a pair of gate offset regions 20 respectively disposed between the source region 17 and the channel forming region 18 and between the channel forming region 18 and the drain region 19; these offset gate regions 20 alleviate any electric field concentrations occurring at and near the boundaries of the regions 17, 18 and 19 (and particularly at and near the boundary separating the drain region and the channel forming region) and in this way the structure aims to realize a high withstand voltage and a low leak current characteristic.
Although the term “a channel forming region” is defined for the purpose of the present invention as a region of a TFT where a channel is formed, it does not necessarily mean that the entire region becomes a channel. In general, it is thought that a channel is formed to a thickness of several hundred Amstrongs at and near the surface that faces the gate electrode through the gate insulator film (in FIG. 1, the interface of the channel forming region 18 and the gate insulation film 14).
Although like the channel forming region the offset gate regions 20 do not positively possess any single conductivity type, because they are not directly affected by the electric field of the gate electrode 15 of the device they each operate as a kind of buffer region which functions neither as a channel nor as a source/drain region. Although not described in detail here, in an LDD structure (Light Dope Drain structure) a high withstand voltage and a low leak characteristic are realized by causing a region between the channel forming region and the drain region which has been lightly doped with an impurity that imparts a conductivity type to function as a buffer so that any electric field concentration occurring at or near the boundary of the channel forming region and the drain region of the device is alleviated.
The structure of the gate offset type TFT mentioned above will now be described, with reference to FIG. 1. The TFT shown in FIG. 1(E) comprises a glass substrate 11, a silicon oxide base film 12, a source region 17, a channel forming region 18, a drain region 19, a silicon oxide film 14 which is a gate insulation film, a gate electrode 15, an interlayer insulation film 16, a source electrode 21, a drain electrode 23 and offset gate regions 20.
With a TFT having the configuration illustrated in FIG. 1(E), the provision of the offset gate regions 20 to alleviate any concentrations occurring in the electric fields at and near the boundaries of the regions 17, 18 and 19 (and particularly near the boundary of the channel forming region 18 and the drain region 19) when the source and the drain of the device are subjected to an electric field can realize a significant reduction in the leak current.
However, while the offset gate regions 20 can sufficiently contribute to improvement of the withstand voltage between the source and the drain, they themselves have a high resistance because they are made of a non-doped semiconductor. Thus, with the configuration illustrated in FIG. 1(E), the offset gate regions 20 operate as parasitic resistors connected in series to the channel forming region 18 and significantly lower the ON current (the drain current that runs between the source and the drain when the TFT is ON).
In other words, with the structure shown in FIG. 1(E), there is the dilemma that although it is possible to realize reductions in the leak current, the ON current falls. As a result, problems such as reduced ON/OFF ratio and reduced field effect mobility, which accompany reductions in the mutual conductance, newly arise, and it is not possible to obtain an entirely satisfactory TFT.
When on the other hand an LDD structure is adopted, although the field effect mobility is reduced to a lesser extent compared with the case of the gate offset structure, because the alleviation of the electric field concentration at the drain region end is not satisfactory, the leak current does not decrease sufficiently, and consequently, as in the case of the gate offset structure, it has not been possible to achieve a satisfactory performance improvement.
FIGS. 1(A) through (E) illustrate different steps in the manufacture of a TFT having a conventional offset gate structure. In this example, vapor phase methods are used for all the film-forming. Items (A) through (E) in the following description roughly correspond to the steps illustrated in FIGS. 1(A) through (E).                (A) A silicon oxide base film 12 is formed on a glass substrate 11 and then a non-crystalline silicon film is formed thereon. Then this non-crystalline silicon film is turned into a polycrystalline silicon film (hereinafter denoted by reference numeral 13) by either thermal solid phase growth or laser annealing.        (B) The polycrystalline silicon layer 13 is processed by photolithography and dry etching into an island shape so that an active layer island is formed. A silicon oxide film 14 is then formed thereon to serve as a gate insulation film.        (C) An impurity-doped non-crystalline silicon film is formed on the silicon oxide film 14 and then by activation by heat and excimer laser it is crystallized and its resistance is reduced. It is then processed by photolithography and dry etching to become a gate electrode 15.        (D) On top of this, a silicon oxide film 16 for forming offset regions is formed.        (E) The silicon oxide film 16 for forming offset regions is etched down to the interface with the gate electrode 15 by anisotropic etching to produce a silicon oxide film wall on the sides of the gate electrode 15 (the side surfaces of the gate electrode 15), and a source region 17 and a drain region 19 are then formed in a self aligning manner by through doping using high output ion doping.        
In this process, since there is a wall of doping stopper (consisting of the silicon oxide film 16 on the side surfaces of the gate electrode 15) at the sides of the gate electrode 15, the areas below the wall are not doped and consequently highly resistive gate offset regions 20, not subject to the gate electric field, are formed respectively between the channel forming region 18 and the source region 17 and between the channel forming region 18 and the drain region 19.
However, in step (E) of the above process, when the silicon oxide film 16 is etched, because non-uniformity of the etching surface becomes a problem, the thickness of the silicon oxide film 16 on the side surface of the gate 15, which determines the offset distance, is not constant over the substrate surface, and when a number of TFTs are made on the surface of the same substrate it is difficult for a uniform offset distance to be obtained over the surface of the substrate.
Also, it is necessary for the lower crystalline silicon layer 13 to be through doped by way of the silicon oxide film 14 with ions of an element selected to impart a single conductivity type, and because compared to a case where the semiconductor layer is doped directly it is necessary to use a higher accelerating voltage, the doping efficiency is reduced, marked damage such as loss of crystallinity is suffered by the crystalline silicon layer 13, and reduced reliability is likely to result.
As described above, although a conventional gate offset structure TFT has the merits that it is possible to improve the withstand voltage between the source and the drain and reduce the leak current (the OFF current), there are the problems of reduced ON current, lowered mutual conductance and reduced field effect mobility, and also, in the process of manufacturing such a device, compared with the manufacture of a self alignment type TFT, there are an increased number of process steps and greater variation in quality and poorer yield; these devices have therefore not always been ideal.
It is therefore an object of this invention to provide a TFT having the following features which it has not been possible to obtain with conventional gate offset structure type and LDD structure type TFTs:
(a) reduced leak current (OFF current), without reduced ON current, and
(b) a simple manufacturing process, with no reduction in yield, and a method for manufacturing such a TFT.